On Regularity and Integrated DFM Metrics

Transistor geometries are well into the nanometer regime, keeping with Moore's Law. With this scaling in geometry, problems not significant in the larger geometries have come to the fore. These problems, collectively termed variability, stem from second-order effects due to the small geometries themselves and engineering limitations in creating the small geometries. The engineering obstacles have a few solutions which are yet to be widely adopted due to cost limitations in deploying them. Addressing and mitigating variability due to second-order effects comes largely under the purview of device engineers and to a smaller extent, design practices. Passive layout measures that ease these manufacturing limitations by regularizing the different layout pitches have been explored in the past. However, the question of the best design practice to combat systematic variations is still open. In this work we explore considerations for the regular layout of the exclusive-OR gate, the half-adder and full-adder cells implemented with varying degrees of regularity. Tradeoffs like complete interconnect unidirectionality, and the inevitable introduction of vias are qualitatively analyzed and some factors affecting the analysis are presented. Finally, results from the Calibre Critical Feature Analysis (CFA) of the cells are used to evaluate the qualitative analysis

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters

Good layout quality is very important in order to obtain efficient Integrated circuits, and custom design methods are thus considered when speed, power, and area requirements are very strict. But since custom design styles require extensive and specialized development resources, automated, less optimal design methods are often chosen. Alternate methods to create efficient layouts may prove useful, especially since custom layout In future technology nodes is associated with prohibitive nonrecurring engineering (NRE) costs. The prototype layout generation environment shown In this paper allows us to define, evaluate and modify fine-grained cell placement strategies for barrel shifters In a quick manner. The three different 90-nm shifter circuit Implementations demonstrated here show a performance that Is on par with circuits harnessing the capabilities offered by conventional tools. Furthermore, this performance is achieved using the least possible die area. For example, a 32-bit fan-out split shifter conventionally laid out and clocked at 1.11 GHz, dissipates 0.37 mW of switching power and occupies an area of 5698 μm2. The same shifter circuit placed using our environment and routed conventionally, equivalently dissipates 0.34 mW, but occupies only 4711 μm2. \ua9 2010 IEEE

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect

A general-purpose datapath is designed for efficient execution of diverse applications. An embedded processor, typically working with a limited application domain, does not necessarily utilize the fixed, general-purpose datapath interconnect efficiently. If we consider the interconnect to be a flexible resource, the datapath can be fine tuned to an application domain. The addition of an interconnect link between two datapath units has the potential to reduce execution time, while the removal of an unused link can save area and power dissipation. Finding the most energy-efficient datapath interconnect configuration for a software application domain is a time-consuming process, since it involves rescheduling of the targeted application(s) on different datapath implementations. We present an automated optimization engine that is based on a genetic algorithm. This engine aids the designer in finding the most energy-efficient interconnect configuration of a simple processor datapath. We show that an optimized datapath interconnect can offer an energy saving of 38% with respect to a general-purpose datapath reference, if the interconnect links are matched to the need of one application

FlexDEF: Development Framework for Processor Architecture Implementation and Evaluation

Designing a processor is a complex task that uses multiple and varied tools. The complete development cycle spans software as well as hardware design and verification. More often than not, in spite of the close dependencies between hardware and software, there is no common platform for quick and accurate testing of these dependencies. Though such systems are often employed in industry, it is not common for end-to-end frameworks to be deployed in educational and research settings. We present the FlexCore Design Exploration Framework (FlexDEF), an end-to-end tool-chain used to develop the FlexCore processor and its accompanying cache system. The tool-chain is a hierarchically linked system that spans the various development phases involved in design and verification. The processor system is intended to be a model, for use in research-oriented projects where both the software and hardware are in a constant state of flux. We discuss the complete framework and the advantages in each context. Finally, we summarize the developments and discuss the future of the FlexDEF tool-chain